A. Field of the Invention
The present invention relates to a semiconductor device used in an internal combustion engine igniter.
B. Description of the Related Art
A circuit shown in FIG. 2 includes primary side coil 45, which is an inductive load, and secondary side coil 42, and functions to cause an intermittent spark to be emitted by means of a high voltage generated in secondary coil 42 in response to an intermittent current flowing from power source 41 to primary side coil 45. As a product to which the circuit is applied, there is an internal combustion engine igniter (which may hereafter be referred to as an “igniter”) that utilizes an intermittent spark emitted in internal combustion engine spark plug 44 connected to secondary side coil 42. To date, a bipolar transistor has been used in the internal combustion engine igniter (igniter) as switching unit 43 to cause the intermittent current to flow to the primary side coil, but in recent years this has been replaced with an insulated gate bipolar transistor (IGBT) (JP-A-2000-310173, JP-A-2002-4991, and Japanese Patent No. 4,263,102). In an IGBT used in this kind of igniter, as well as control circuit portion 21 for preventing the IGBT being destroyed due to an overcurrent, an overvoltage, or heat generation being built in, as shown in an IGBT main portion sectional view of FIG. 5, gate control circuit portion 17 shown in an equivalent circuit of the IGBT of FIG. 3 may be built in so that the IGBT has a function of monitoring an operational condition, and controlling a gate signal when there is an abnormality.
In order to reduce a surge voltage when an L load is turned off, it is known to provide an n-type region with an intermediate impurity concentration between a high resistance n-type base layer and a high impurity concentration n-type buffer layer of the IGBT (Japanese Patent No. 4,164,962 and JP-A-6-268226). Also, in order to prevent the IGBT from being destroyed by a surge voltage with a collector side as negative, generated in an L load circuit when the IGBT is turned off, there is known an IGBT configured to provide a collector region positioned on the collector side opposed to a front side IGBT region (JP-A-2009-105265). Also, in order to make it difficult for the IGBT to be destroyed by a surge voltage with a collector side as negative, generated in an igniter circuit when the IGBT is turned off, an IGBT is also commonly known that has an n-type buffer region with a p-n junction withstand voltage higher than an automobile battery voltage in a collector side p-n junction interface (JP-A-2009-130096). There also is a description relating to an IGBT wherein an n-type buffer layer is a two-layer configuration of differing impurity concentrations (Japanese Patent No. 3,764,343).
In the igniter inductive load circuit (FIG. 2), in a process wherein the current decreases sharply when the IGBT switches from an on condition to an off condition, a voltage in a direction (the IGBT collector side is the positive direction) that, in response to a coil inductance L and a change in a current flowing through the coil, suppresses the change rises sharply in primary side coil 45, and on the IGBT reaching the off condition, the voltage drops sharply. When the suddenly generated surge voltage (a few hundred volts) is clamped by a zener voltage of zener diode 16 (FIG. 3) disposed between the collector gates of the IGBT, the primary side coil voltage is induced in the secondary side coil, a reverse direction voltage is generated in the secondary side coil, a discharge is started, and energy accumulated in the inductor is released.
However, in the event that the discharge does not take place for some reason, it may happen that the energy accumulated in the inductor returns directly to the IGBT side, and a situation occurs wherein the IGBT itself has to consume the energy. A condition at this time is shown in FIG. 4. The horizontal axis shows time, and the vertical axis current or voltage. That is, on a voltage Vc generated on the collector side reaching a clamp voltage Vb of the diode between the gate and collector, the voltage is clamped, the gate voltage is positively biased by the current flowing through the diode flowing through gate resistor 36 in FIG. 3, the IGBT attains the on condition, and a current flows. While maintaining this condition, the current continues until 0 in a condition in which the large voltage Vb is applied to the IGBT. During this time, even in the event that the internal temperature of the IGBT rises due to a large incurred loss, the IGBT needs to withstand this without breaking down. A maximum incurred loss energy amount at this time is called an energy withstand. Unless there is a device breakdown due to a localized heat generation such as a latch-up caused by the configuration or structure of the circuit or IGBT, an energy amount reaching a physical thermal breakdown temperature as a silicon semiconductor is the limit of the energy withstand. For this reason, the capacity increases as a chip size increases. Also, when the radiation of heat to the exterior is good, the temperature rise is suppressed, and the capacity increases. Consequently, the energy withstand is one factor when determining a limit in the event of wishing to reduce the chip size in order to lower the cost of a product. A heretofore known sectional structure of this kind of igniter IGBT is shown in FIG. 5. The IGBT of FIG. 5 includes n+ buffer layer 24 and n base layer 26 on p+ substrate 25, and active region 20 that causes a main current of the IGBT to flow is provided in a central portion of the n base layer surface. The surface of active region 20 includes an emitter electrode to which p base region 6, n emitter region 7, gate insulating film 13, gate terminal 2, gate electrode 14, and emitter terminal 3 are connected, and the like. Pressure resisting region 18 is disposed in a periphery encircling active region 20. Control circuit portion block 21 including a horizontal MOSFET is monolithically formed of channel region 9, source 10-1, drain 10-2, gate oxidizing film 11, gate electrode 12, and the like, on the right side of active area 20 in FIG. 5. P region 8 is a region for, by short circuiting with the emitter electrode, reducing a current flowing to the circuit portion 21 by transferring a current flowing into channel region 9 to the emitter electrode, and protecting the IGBT from an element breakdown due to a parasitic current. From a manufacturing aspect, it is often the case that clamping diode 16 connected between gate 2 and collector 1 of the IGBT is formed of a polysilicon layer deposited across an insulating film on the IGBT substrate surface in such a way that a current flows along the surface.
Meanwhile, with an automobile ignition device such as an igniter, when a 12V power source of a battery mounted in an automobile is carelessly turned off, there is a mode wherein, as a current flowing through a load inductor decreases sharply, the inductor generates a reverse bias voltage (−Ldi/dt), as previously described. At this time, there is a demand for a reverse surge withstand capability (V) whereby there is no breakdown even when there is a reverse voltage and a current flows in the switching semiconductor element (IGBT). FIG. 7 shows a testing circuit that applies a reverse surge voltage. Capacitor 48 is charged from power source 49, and a current is caused to flow by switching this to the semiconductor side. At this time, a voltage equal to or greater than a reverse withstand voltage is applied to the IGBT, which is a semiconductor element, a current flows, and energy accumulated in the capacitor is released. The charging voltage at this time is called the reverse surge withstand capability (V). FIG. 6 shows a condition in the interior of the IGBT at this time, using FIG. 5. The reverse withstand voltage of the IGBT is determined by withstand voltage characteristics of a p-n junction (diode 19) formed of p-type substrate 25 and the buffer layer 24. On a reverse voltage with the emitter 3 as positive and collector 1 as negative being applied to the IGBT, p-n junction 17 included in active region 20 and control circuit portion 21 on the device surface side attains a forward bias condition, and the current flows at a low voltage. At this time, when it is assumed from FIG. 7 that the dynamic resistance of the IGBT reverse withstand voltage characteristic is 0, the energy consumed by the IGBT is calculated as:
                                          ∫                          P              ⁢                              ⅆ                t                                                          C            C                          =                                            V              B                        ⁡                          (                                                V                  S                                -                                  V                  B                                            )                                -                                                                      R                  1                                ⁢                                  V                  B                                                            (                                                      R                    1                                    +                                      R                    2                                                  )                                      ⁡                          [                                                (                                                            V                      S                                        -                                          V                      B                                                        )                                +                                                                            R                      2                                                              (                                                                        R                          1                                                +                                                  R                          2                                                                    )                                                        ⁢                                      V                    B                                    ⁢                  ln                  ⁢                                                                                                                                  (                                                                                    R                              1                                                        +                                                          R                              2                                                                                )                                                                          R                          1                                                                    ⁢                                              (                                                                                                            V                              S                                                                                      V                              B                                                                                -                                                                                    R                              2                                                                                      (                                                                                                R                                  1                                                                +                                                                  R                                  2                                                                                            )                                                                                                      )                                                                                                                            ]                                                          Equation        ⁢                                  ⁢        1            
P: consumed energy of semiconductor device,
Cc: capacitor capacity,
R1 and R2: circuit resistors (FIG. 7),
VB: IGBT reverse withstand voltage,
Vs: capacitor charging voltage
As is understood from the equation, the consumed energy decreases as the IGBT reverse withstand voltage VB decreases. This is because the resistor R1 connected in series with the IGBT, and the resistor R2 connected in parallel, consume the rest of the energy. The lower the IGBT reverse withstand voltage VB, the more the reverse surge withstand capability (V) increases. This is shown in FIGS. 8 and 9, with FIG. 8 showing a relationship between the impurity concentration of IGBT buffer layer 24 and the reverse withstand voltage, and FIG. 9 showing a relationship between the reverse withstand voltage and the reverse surge withstand capability when actually measured. For this reason, it is necessary to lower the reverse withstand voltage in order to secure the reverse surge withstand capability. However, in an automobile application, it is required that the semiconductor does not break down even in the event that the battery is accidentally connected with the polarities reversed. For this reason, a reverse withstand voltage at least as high as the battery voltage (12V) is required. As it may happen that two batteries are used in series, a design is necessary wherein the reverse withstand voltage is at least 30V, and when considering reverse withstand voltage fluctuation and the like, 40V. For this reason, it is necessary to secure the reverse surge withstand capability while making the reverse withstand voltage a minimum of around 40V.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.